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IS61LV256
32K x 8 LOW VOLTAGE CMOS STATIC RAM
.EATURES
High-speed access times: -- 8, 10, 12, 15, 20 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mW (max.) operating -- 7 mW (max.) CMOS standby TTL compatible interface levels Single 3.3V power supply .ully static operation: no clock or refresh required Three-state outputs
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 W (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300mil SOJ and the 8*13.4mm TSOP-1 package.
DESCRIPTION The 1+51 IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using 1+51's
.UNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
256 X 1024 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
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IS61LV256
PIN CON.IGURATION
28-Pin SOJ
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
PIN CON.IGURATION
8x13.4mm TSOP-1
VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
PIN DESCRIPTIONS
A0-A14 CE OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB, ISB ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TBIAS TSTG PD IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value 0.5 to +4.6 0.5 to +4.6 10 to +85 45 to +90 65 to +150 1 20 Unit V V C C W mA
Com. Ind.
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Integrated Circuit Solution Inc.
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IS61LV256
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C 40C to +85C Speed 8, 10, 12 15, 20 All VCC 3.3V, +10%, 5% 3.3V 10% 3.3V + 10%, 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = 4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 2.2 0.3 1 5 1 5 Max. 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V A A
Notes: 1. VIL (min.) = 0.3V (DC); VIL (min.) = 2.0V (pulse width 2.0 ns). VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width 2.0 ns). 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Sym. Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE VIH, f = 0 VCC = Max., CE VCC 0.2V, VIN > VCC 0.2V, or VIN 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
-20 ns
Min. Max. Unit
120 130 25 30 2 5
110 120 25 30 2 5
100 110 25 30 2 5
90 100 25 30 2 5
80 90 25 30 2 5
mA mA
ISB
mA
Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 5 Unit p. p.
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
Integrated Circuit Solution Inc.
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IS61LV256
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time
Min. Max.
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
-20 ns
Unit
tRC tAA tOHA tACE tDOE tHZOE tLZCE tPU! tPD
"
8 2 0 3 0
8 8 4 4 4 8
10 2 0 3 0
10 10 5 5 5 10
12 2 0 3 0
12 12 6 5 6 12
15 2 0 3 0
15 15 7 6 7 15
20 2 0 3 0
20 20 8 6 7 20
ns ns ns ns ns ns ns ns ns ns ns
tLZOE OE to Low-Z Output
OE to High-Z Output CE to Low-Z Output CE to Power-Up CE to Power-Down
tHZCE CE to High-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in .igure 1. 2. Tested with the load in .igure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and .all Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See .igures 1 and 2
AC TEST LOADS
319 3.3V
3.3V 319
OUTPUT 30 pF Including jig and scope 353
OUTPUT 5 pF Including jig and scope 353
.igure 1. 4
.igure 2. Integrated Circuit Solution Inc.
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IS61LV256
AC WAVE.ORMS READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
DATA VALID
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Circuit Solution Inc.
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IS61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width(OE High) WE Pulse Width(OE Low) Data Setup to Write End Data Hold from Write End
!
Min. Max.
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
-20 ns
Unit
tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE
!
8 7 7 0 0 7 6.5 4.5 0 0
3.5
10 8 8 0 0 10 7 5 0 0
4
12 8 8 0 0 12 8 6 0 0
6
15 10 10 0 0 15 10 7 0 0
7
20 12 12 0 0 20 12 10 0 0
7
ns ns ns ns ns ns ns ns ns ns ns
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in .igure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in .igure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVE.ORMS WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t WC
ADDRESS
VALID ADDRESS
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t HZWE t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
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Integrated Circuit Solution Inc.
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IS61LV256
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE CE
LOW
t HA
LOW
t AW t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH.
Integrated Circuit Solution Inc.
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IS61LV256
ORDERING IN.ORMATION Commercial Range: 0C to +70C
Speed (ns) 8 10 12 15 20 Order Part No. IS61LV256-8T IS61LV256-8J IS61LV256-10T IS61LV256-10J IS61LV256-12T IS61LV256-12J IS61LV256-15T IS61LV256-15J IS61LV256-15T IS61LV256-20J Package 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ
ORDERING IN.ORMATION Industrial Range: 40C to +85C
Speed (ns) 8 10 12 15 20 Order Part No. IS61LV256-8TI IS61LV256-8JI IS61LV256-10TI IS61LV256-10JI IS61LV256-12TI IS61LV256-12JI IS61LV256-15TI IS61LV256-15JI IS61LV256-20TI IS61LV256-20JI Package 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ 8*13.4mm TSOP-1 300mil SOJ
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000
Integrated Circuit Solution Inc.
BRANCH O..ICE: 7., NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw
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